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Some Bibliographies of CAD, Codesign and Architecture, Sensor Networks
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Well categorized Bibtex Bibliography for CAD, Codesign etc for Digital Circuits and Systems
(or download the bibtex file): Latest update March 19, 2003
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Bibliography for CAD for Digital Circuits and Systems by
Rajesh Gupta
(from 1996 but very good)
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Hardware/Software Codesign Bibliography
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Another Hardware/Software Codesign Bibliography by Kiyoung Choi
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BibTeX of Computer Architecture readings for the PhD qualifier by Ali Dasdan
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Searchable Computer Science Bilbiography
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Bibliography of Computer Architecture Conferences
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BibTeX of Asynchronous Design and Synthesis
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Bibliography of CAD, Synthesis
- Well
Categorized Wireless Ad Hoc Networks Bibliography
- Sensor Network
and Security Bibliography
| Project | Areas of Interest |
| Chinook | Hw/Sw co-synthesis CAD tool for embedded systems |
| Cinderella | Program Timing Analysis Tool |
| CodeSign | Design of embedded real time sytems |
| Esterel | Synchronous Reactive Programming Language |
| GRAPE II | System-Level Design Tools for DSPs |
| POLIS | Unified Hw/Sw Codesign |
| Ptolemy | Design of reactive systems |
| RASSP | Rapid-Prototyping of Application Specific Signal Processors |
| Rosetta | A Systems Level Design Language |
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SPARK | UC Irvine's C-based High Level Synthesis project which adapts parallelizing compiler technology for synthesis |
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SynDex | INRIA's Real-time Embedded Applications tool |
| Univ Group | Areas of Interest |
| CMU's Center for Electronic Design Automation | Codesign, Benchmarks, DSP |
| Integrated Signal Processing Systems | DSPStone, SPAM, Fridge, DSP compilers |
| A. Jerraya's System-Level Synthesis Group | hardware/software co-design, system level synthesis |
| UCLA Papers Library | Intl Collection of Technical Reports and Papers |
| Rajesh Gupta's Group (iESAG) | Hw/Sw Co-design of Embedded Systems |
| G. Micheli's Synthesis Group | Many aspects of CAD, Synthesis, Hw/Sw Co-Design |
| Stanford Electronic Library | Searchable Tech Reports, Pubs etc |
| Tech Univ of Braunschwirg | COSYMA, Prototyping, Embedded Systems |
| UC Berkeley CAD Home Page | All aspects of CAD |
| UCI's Center for Embedded Computer Systems | Embedded Systems, Hw/Sw Co-design, HDLs |
| UCLA VLSI CAD Lab | VLSI CAD |
| UCSB CAD & Test Group | CAD & Test Group |
| Research Lab | Areas of Interest |
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IMEC's SOC++ System Design IMEC's Reconfigurable Systems Program |
System level C++ based design, Hardware & Software Synthesis |
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INRIA's Codesign Project |
Implementing systems on silicon List of INRIA's other Research Activities |
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IBM's Verification Group |
Sugar Spec Language for property checking Formal Checkers |
| People | Areas of Interest |
| Guido Araujo | Compilers, Code Generation for Embedded Systems |
| Peter Beerel | Mixed Asynch/Synchronous Arch Synthesis |
| Gaetano Borriello (pubs) | Embedded Systems, Design automation, Real-time Systems |
| Forrest Brewer | VLSI/Comp Sys CAD, High-Speed Logic Design |
| Pai Chou | System-level design for Power, Medical Embedded Systems |
| Jason Cong | VLSI CAD, FPGAs |
| Srinivas Devadas | CAD, Code generation, test generation, verification |
| Sujit Dey | Hw-Sw Embedded System-on-Chip Design, VLSI CAD, Testing |
| Nikil Dutt | Retargetable compilers, memory issues & design automation in embedded systems |
| Rolf Ernst | Embedded Systems Design Automation |
| Daniel Gajski | Embedded Systems Methodology, Specificaion, IP Reuse |
| Rajesh Gupta | Hw/Sw Co-design, software synthesis, timing analysis, adaptive systems |
| Soonhoi Ha | Codesign, Design methodology |
| Ahmed Jerraya | Codesign, System design, Arch Synthesis |
| Niraj K. Jha | Digital System Testing, CAD, Hw/Sw Co-Synthesis |
| Philip Koopman | Affordable Dependability & Embedded Systems |
| Fadi Kurdahi | VLSI CAD - High Level Synthesis |
| Luciano Lavagno | Hw/Sw Co-design, Async Design & Testing |
| Edward A. Lee | Embedded systems, Real-time software |
| Rainer Leupers | Embedded systems Compilers, Code Generation |
| Bill Lin | Sys-Level DA, Multimedia systems design |
| Vijay Madisetti | Rapid Prototyping |
| Sharad Malik | Embedded Systems & Software, Software Synthesis |
| Peter Marwedel | Hw/Sw Partitioning and Code Generation/Synthesis |
| Giovanni De Micheli | Low Power Synthesis, Hw/Sw Co-Design |
| Ralph Otten | Hw/Sw Partitioning and Code Generation/Synthesis |
| Miodrag Potkonjak | IP watermarking, synthesis, VLSI CAD |
| Jan M. Rabaey | Embedded Sys, Low Power & System design tools |
| Jonathan Rose | FPGAs, CPLDs arch., chip design, CAD |
| Majid Sarrafzadeh | Reconfigurable Computing, Low-Power Embedded Systems |
| Frank Vahid | Hw/Sw Co-design of Embedded Systems |
| Wayne Wolf | Co-design of Embedded Systems, Video Arch |
| Kenneth Y. Yun | Mixed-Time VLSI System Synthesis |
| Benchmark Sources | Areas Covered |
| List of All benchmarks I have | HLS, DSP, HardwareC, DSPstone, UT Toronto, Spam etc. Contact me if you want a pointer on how to get each othese. |
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1995 High-Level Synthesis Design Repository 1992 High-Level Synthesis Design Repository |
HLS Benchmarks collected by Dutt and Panda |
| MiBench: Good Embedded Benchmark Suite | Automotive, Consumer, Network, Office, Security, Telecomm |
| MediaBench: Media Applications | Mpeg, Gsm, PGP, G.721 etc |
| CommBench: Telecommunications Network Processor Applications | DRR, FRAG, RTR, TCP, etc |
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MD5 Crypto Reference Code NetBench Benchmark Suite | Network Benchmarks |
| Compression Algorithms Source Code Page | Source for everything ranging from compression, audio, mpeg, image |
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1.
Speech Related Software 2. Another from comp.speech.faq |
Coding, Synthesis, Recognition |
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Image Processing & Graphics Source Codes Open source GIMP Image Processing Tool |
Many, many pieces of computationally expensive graphics code |
| Video Coding Simulation Models | H.261, H.263, Mpeg-1, Mpeg-2 |
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DSPstone benchmark suite SPAM benchmark suite U. of Toronto benchmark suite |
DSP benchmarks (for compilers etc) |
| Spark's High Level Synthesis Benchmark Repository | C files for MPEG, ADPCM etc which can be synthesized by the Spark High Level Synthesis system |
| Embedded Microporcessor Benchmark Consortium | Certifies real-world benchmarks |
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CMU DSP: Synthesizable Processor SUN's picoJava Core SUN's microSparc Core OpenRisc Processors w/ Compiler ESA's Leon Sparc-Compatible Processor Synthesized Leon Sayuri 32 bit processor Pancham MD5 Cryptography Core DSP,RISC, DMA for Structured ASICs |
Synthesizable Cores/IP |
| DIMACS benchmark challenge | Graph coloring instances |
| Collection of Open Source Hardware Designs | The Open Collector: Free EDA software and circuit designs |
| comp.benchmarks repository | All kinds of benchmarks and CPU info |
| Task Graphs For Free(TGFF) | Generates random task graphs for scheduling/allocation |
| Embedded System Synthesis Benchmarks Suite | Consists of about 17 processors |
| Links & Resources | Areas Covered |
| ACM DA Pubs Page | Complete DAC, ICCAD, ISLPED, ISSS, Euro-DAC Proceedings Archive |
| Sigda Home Page | DAC, ICCAD & TODAES Proceedings Archive |
| Sigda Pubs on CDROM | Complete list of Sigda Pubs on CDROM |
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Links to upcoming conferences Parallel computing conferences |
Submission deadlines of upcoming conferences |
| Links to projects, tutorials, researchers in Design, Design automation | List of links here is well maintained and ever expanding |
| Embedded Systems Internet Resources | Software, Links, newsgroups |
| Hw/Sw Co-Design Research Links | Links to other groups, researchers etc |
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SIGDA's Links to CAD Sites Links to all kinds of Electronics sites |
Well categorized links to Academic and Industry sites |
| Ralf Niemann's links to Codesign Projects | Links to groups & projects in codesign |
| DAC Cafe | News etc on EDA |
| Design & Reuse Website | directory for designing systems on chip |
| Excellent VHDL Resource Website | Check out the Testbench Generator |
| VHDL Cookbook on the net | VHDL book on the net, VHDL resources |
| VLSI Design Book on the net | Design of VLSI Systems by D. Mlynek, Y. Leblebici |
| ASICs ... the book - Alternate Link | ASIC design book on the net by Michael John Sebastian Smith |
| Arithmetic Module Generator | Generates VHDL/Verilog code for any given input widths, with(out) truncation/accumulate |
| GPL Electronic Design Automation | Some EDA tools available open source under GPL |
| VLSI Resource Center | Links to VLSI resources on the internet |
| Logic Synthesis Links | ASIC Synthesis, Hands-on Synthesis and Simulation Verilog/ASIC/Design Resources |
| Links to researchers | Links to Computer architecture, compilers and VLSI CAD researchers with photographs and areas of research |
| ChipWorks | Company specializing in reverse engineering chips and software |
| Tensilica | Company specializing in configurable processor cores and standard processor cores |
| Embedded System/Codesign Course Web Pages |
| Introduction to Embedded Computer Systems | Rajesh Gupta, UC Irvine |
| Software for Embedded Systems | Rajesh Gupta, UC Irvine |
| Computer Aided Design of Digital Circuits and Systems | Rajesh Gupta, UC Irvine |
| Distributed Embedded Systems | Phil Koopman, CMU |
| Design of Embedded Systems: Models, Validation, and Synthesis | A. Sangiovanni-Vincentelli, UC Berkeley |
| List of Embedded/Real-Time Embedded Systems Courses maintained by Frank Vahid | Frank Vahid, UC Riverside |
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Relatively simple guides for Understanding the Microprocessor Understanding Pipelining and Superscalar Execution |
Jon Stokes, Ars Technica |