Where abouts
| Currently at | NVIDIA: Tesla GPU Computing Group |
| Doing | Product Marketing |
| sumitg at gmail.com | |
| Education | B.Tech., EE, IIT Delhi, 1995 Phd, CS (Embedded Systems), UC Irvine, 2003 |
| Resume | SumitResume.pdf |
Biography
The gamut of my work and research experience ranges from being an ASIC designer to writing compilers to doing product marketing. I have written large software tools -- the SPARK synthesis tool is 100K+ lines of C++ code -- and large hardware descriptions -- specifically, the RTL description of the data path of the media processor and the custom design of a complex SIMD 32-bit multiplier.
Life as I remember it started in Kuwait (although I was born in Bhilai, Madhya Pradesh, India). I studied at the Indian School, Kuwait till the Iraqi invasion of Kuwait, after which I spent my "refugee" days in Delhi. I completed my high school at Mother's International School, Delhi in 1991.
I then went on to pick up a B.Tech in Electrical Engineering in 1995 from IIT Delhi (Indian Institute of Technology Delhi). (You can register yourself at this site, if you are an IIT Delhi Alumnus and at the IIT Delhi Alumni Association web page.)
After undergrad school, I spent a few months working as a Software Engineer at IBM Global Services, in Bangalore India. I then moved to a startup (as employee 5) called S3 India, where I worked on ASIC design as part of a media processor design team. I also did some part-time research with Prof Sriram Vajapeyam at SERC, Indian Institute of Science, Bangalore during the 1996-1997 time frame.
I then went on to do my Phd from the School of Information and Computer science at UC, Irvine. For my Ph.D., I worked on the crossroads of compiler technology and embedded system design and design automation. I (with a little/lot of help from my friends) built a C-based parallelizing high-level synthesis framework called SPARK. The novel parallelizing high-level synthesis methodology that we developed for SPARK presents a leap forward in improving the quality of results for high-level synthesis. My Ph.D. advisor was Prof Rajesh Gupta, who heads the Microlectronic Embedded System Lab lat the Computer Science and Engineering Dept, at the University of California at San Diego. Next, I did Post-doctoral research at the Center for Embedded Computer Systems on reconfigurable computing and system-level design and synthesis at UC San Diego & UC Irvine.
Next, I spent a year at Tallwood Venture Capital, where I analyzed technological innovations and market forces in the reconfigurable, FPGA, and programmable spaces. I explored technological innovations impacting this space and the market forces shaping demand for these technologies. The aim was to determine an investment strategy for Tallwood VC in this space. I spent a particularly long time looking at FPGAs --both on how we could innovate on FPGA architectures and what were the table-stakes and barriers to entry into this market. I also helped in due diligence of startups/business plans that came into the firm. This included both technical and marketing due diligence. Note that Tallwood is a VC focused soley on early stage startups in the semiconductor space.
I till recently was Product Manager doing both inbound product management
and outbound product marketing at Tensilica, which markets configurable and extensible processor IP cores called the Xtensa processor core along with fixed Diamond Standard Cores.
I worked on all aspects of inbound and outbound marketing, including defining the feature set of our current
and future products, creating sales collateral, mananging veritical video and system-level products and strategy, et cetera. Previously, I worked on customer designs to enable customers to maximally use the configurability options of Tensilica's Xtensa core.
I am now a product manager in the
Tesla GPU Computing group
at NVIDIA. NVIDIA's GPUs have evolved over the years to become massively parallel computing machines with huge arrays of parallel processing elements, thereby, leading to this effort. The same floating point performance that is useful for graphics is also useful for scientific, technical, biological, imaging, and financial computing.
During the summer of 1998, I interned with the VLSI Systems Design and Methodologies group at IMEC in Leuven, Belgium. During the same summer, I also travelled through several parts of Europe (needless to say that was fun !). In the summer of 2001, I interned with the Strategic CAD Labs at Intel, in Portland, Oregon. Oregon is a beautiful state with lots of outdoor activities and sights.
On the lighter side, I enjoy outdoor sports and am (was) into rock climbing, tennis, hiking. My last passion (before I became a family man) was Aikido with Sensei Haruo Matsuoka. I have also learnt some Wushu from Sifu Vadim Zukhov.
